COMPUTER ARCHITECTURE AND PARALLEL PROCESSING MODEL EXAM QUESTION PAPERS

Roll No:

Programme     :  ME Branch             :  Electronics and Communication Engineering  (VLSI Design) Semester        :  II	Date:      .05.2013 Time:  9.30 am  to 12.30 pm
Course Code:  AP9222 Course Name: COMPUTER ARCHITECTURE AND PARALLEL   PROCESSING	Duration : 3Hours Max. Marks   : 100

                                                                                        

PART-A (10 x 2 = 20 MARKS)

ANSWER ALL THE QUESTIONS

1.	In parallel computing, what are shared memory-multiprocessors and distributed-memory multicomputers?
2.	Mention an approach to solve the mismatch problem between software parallelism and hardware parallelism.
3.	What is grain packing and scheduling in parallel programming that can help achieve a short schedule for fast program execution?
4.	What scalability metrics affect the scalability of a computer system for a given application?
5.	List the characteristics of CISC, RISC and Superscalar processors.
6.	How are sequential consistency and weak consistency memory models characterized?
7.	Distinguish between asynchronous and synchronous pipeline models.
8.	Distinguish between static dataflow and dynamic dataflow computers.
9.	Differentiate time-sharing and space-sharing operating systems.
10.	What are macrotasking, microtasking and autotasking levels of multitasking employed for parallel execution on Cray X-MP or Y-MP multiprocessors?

PART-B (5 x 16 = 80 MARKS)

ANSWER ALL THE QUESTIONS

11.	(a)	Discuss how the instruction set, compiler technology. CPU implementation and control, cache and memory hierarchy affects CPU performance. Justify their effects in terms of program length, clock rate and effective cycles per instruction (CPI).	(16)
		(OR)
	(b)	Compare the PRAM and VLSI models of parallel computers and mention how these models facilitate the study of asymptotic behavior of algorithms implementable on parallel computers.	(16)
12.	(a)	Discuss the different network architectures used for interconnecting multiprocessor or multicomputer systems highlighting their merits and demerits.	(16)
		(OR)
	(b)	(i) Discuss the three speedup performance models used under different computing objectives and resource constraints.	(10)
		(ii) A web server application running on a single processor is enhanced by a 10 processor parallel computer. The parallel processor is 20 times faster than the original processor, but is available only for 40% of the time. What is the overall speedup gained by incorporating the enhancement?	(6)
13.	(a)	Discuss the design of a memory hierarchy for a computer system satisfying the three properties of inclusion, coherence and locality with due consideration to capacity planning and cost optimization.	(16)
		(OR)
		Discuss briefly the different shared- memory organization techniques employed in computer system to meet the memory design goal of matching memory bandwidth to processor bandwidth.	(16)
14.	(a)	(i) Briefly discuss the instruction pipeline design with reference to instruction processing, data forwarding, hazard avoidance, scheduling and branch handling.	(10)
		A non pipelined processor X has a clock rate of 25 MHz and an average CPI (Cycles Per Instruction) of 4. Processor Y. an improved version of X, is designed with a live-stage linear instruction pipeline. However, due to latch delay and clock skew effects, the clock rate of Y is only 20 MHz. If a program containing 100 instructions is executed on both processors, what is the speed up of processor Y compared with that of processor X?	(6)
		(OR)
		(b) Compare the four context switching policies employed in different multithreaded architectures: switch on cache miss, switch on every load, switch on instruction (cycle by cycle) and switch on block of instructions. (i) What are the advantages and shortcomings of each policy?	(8)
		(ii) How can an optimal choice be made among the four policies?	(8)
15.	(a)	Parallel programming models are specifically designed for multiprocessors, multicomputers, or vector/SIMD computers. Briefly discuss these models that exploit parallelism with different execution paradigms for these computers.	(16)
		(OR)
	(b)	Discuss the use of spin locks, suspend locks, binary and counting semaphores, deadlock prevention, avoidance, detection and recovery schemes and monitors for shared-variable programming to implement various synchronization methods among concurrent processes.	(16)

                                                                                                Roll No:

Programme     :  ME Branch             :  Electronics and Communication Engineering  (VLSI Design) Semester        :  II	Date:     .05.2013 Time:  9.30 am  to 12.30 pm
Course Code:  AP9222 Course Name: COMPUTER ARCHITECTURE AND PARALLEL   PROCESSING	Duration : 3 Hours Max. Marks   : 100

                                                                                        

PART-A (10 x 2 = 20 MARKS)

ANSWER ALL THE QUESTIONS

1.	Compare temporal parallelism and data parallelism.
2.	What is the major difference between multiprocessor and multicomputer?
3.	Define anti dependence and output dependence with respect to parallelism and dependence relations.
4.	Compare control flow and data flow computers in terms of flow mechanism.
5.	Why is memory hierarchy needed?
6.	Define any four scalability merits for an application.
7.	What is a symbolic processor?
8.	State the instruction format used in VLIW process.
9.	Name any two languages supporting parallelism.
10.	Name the phases of parallel compiler.

PART-B (5 x 16 = 80 MARKS)

ANSWER ALL THE QUESTIONS

11.	(a)	(i) Describe Flynn's classification of computers.	(10)
		(ii) Explain the super computer architecture for vector processing.	(6)
		(OR)
	(b)	(i) Explain the various theoretical models of parallel computers. How are they useful in scalability and programmability analysis?	(8)
		(ii) Distinguish between multiprocessors and multi computers based on their structures, resource sharing and inter process communications.	(8)
12.	(a)	(i) Explain the functional structure of a crossbar network and how I/O connections are achieved?	(8)
		(ii) Explain the static data flow computer architecture with a diagram.	(8)
		(OR)
	(b)	(i) Compare the features of static network with dynamic networks. Explain how the interconnection is established for parallel processing.	(10)
		(ii) Define the various speed up performance laws.	(6)
13.	(a)	A two level memory system has five virtual pages on a disk to be mapped Into (i) Two page frames (ii) Three page frames in the main memory. A certain program generated the following page trace. 0, 1, 2, 3, 4, 4, 4, 2, 1, 0, 2, 2, 2, 3, 0. (1) Calculate the hit ratios using FIFO, LRU, circular FIFO and LFU replacement policies on both cases. (2) Indicate which page replacement policy is optimal on both cases. (3) Calculate the improvement or reduction in hit ratio on increase in page frames in main memory.	(16)
		(OR)
	(b)	(i) Describe a four level memory hierarchy technology.	(8)
		(ii) Explain temporal, spacial and sequential locality associated with program/data access in a memory hierarchy.	(8)
14.	(a)	(i) Design a pipe line multiplier to multiply a stream of input numbers X0, X2, X3.... by a fixed number Y. Assume all X's and Y's are 16 bit numbers. Draw a neat schematic diagram of your design.	(12)
		(ii) Compare linear and non linear pipelines.	(4)
		(OR)
	(b)	(i) Explain any one scalable multithreaded architecture with a neat diagram.	(8)
		(ii) Write about the features of data flow architectures.	(8)
15.	(a)	(i) Explain the message based communications in MACH and 0SF/1 systems.	(8)
		(ii) Write a program for matrix multiplication in FORTRAN using its parallel constructs.	(8)
		(OR)
	(b)	Draw and explain the phases of parallel language compilers.	(16)