LESSON
PLAN
Course
Code & Name : CS2253 - COMPUTER ORGANIZATION AND ARCHITECTURE
Faculty :
Class &
Semester : II Year B.E (CSE)
– IV Semester
Sl. No.
|
PROPOSED
|
TOPIC
|
|
DATE
|
PERIOD |
||
1.
|
19.12.2012
|
3
|
Unit – I: Functional
units
|
2.
|
19.12.2012
|
8
|
Basic
operational concepts
|
3.
|
20.12.2012
|
4
|
Bus
structures
|
4.
|
21.12.2012
|
1
|
Performance
and metrics
|
5.
|
26.12.2012
|
3
|
Instructions and instruction
sequencing
|
6.
|
26.12.2012
|
8
|
Hardware - Software Interface
|
7.
|
27.12.2012
|
4
|
Instruction set architecture
|
8.
|
28.12.2012
|
1
|
Addressing modes
|
9.
|
02.01.2013
|
3
|
RISC – CISC
|
10.
|
02.01.2013
|
8
|
ALU design
|
11.
|
03.01.2013
|
4
|
Fixed
point and floating point operations
|
12.
|
04.01.2013
|
1
|
Unit – II: Fundamental
concepts
|
13.
|
09.01.2013
|
3
|
Execution
of a complete instruction
|
14.
|
09.01.2013
|
8
|
Execution
of a complete instruction
|
15.
|
10.01.2013
|
4
|
Multiple bus organization
|
16.
|
11.01.2013
|
1
|
Multiple
bus organization
|
17.
|
18.01.2013
|
1
|
Hardwired control
|
18.
|
23.01.2013
|
3
|
Micro
programmed control
|
19.
|
23.01.2013
|
8
|
Micro
programmed control
|
20.
|
24.01.2013
|
4
|
Nano
programming
|
CYCLE TEST – I (29.01.2013 – 31.01.2013)
|
|||
21.
|
01.02.2013
|
1
|
Nano programming
|
22.
|
06.02.2013
|
3
|
Unit – III: Basic concepts
|
23.
|
06.02.2013
|
8
|
Data
hazards
|
24.
|
07.02.2013
|
4
|
Data
hazards
|
25.
|
08.02.2013
|
1
|
Instruction
hazards
|
26.
|
13.02.2013
|
3
|
Instruction
hazards
|
27.
|
13.02.2013
|
8
|
Influence on instruction sets
|
28.
|
14.02.2013
|
4
|
Influence
on instruction sets
|
CYCLE TEST – II (23.08.2012 – 25.08.2012)
|
|||
29.
|
15.02.2013
|
1
|
Data path
and control considerations
|
30.
|
20.02.2013
|
3
|
Data path
and control considerations
|
31.
|
20.02.2013
|
8
|
Performance
considerations
|
32.
|
21.02.2013
|
4
|
Exception
handling.
|
33.
|
22.02.2013
|
1
|
Unit - IV: Basic concepts
|
34.
|
27.02.2013
|
3
|
Semiconductor
RAM
|
35.
|
27.02.2013
|
8
|
ROM
|
36.
|
28.02.2013
|
4
|
Speed
|
37.
|
01.03.2013
|
1
|
Size and
cost
|
38.
|
06.03.2013
|
3
|
Cache
memories
|
39.
|
06.03.2013
|
8
|
Improving cache performance
|
40.
|
07.03.2013
|
4
|
Virtual
memory
|
41.
|
08.03.2013
|
1
|
Memory
management requirements
|
CYCLE TEST – II (11.03.2013 – 13.03.2013)
|
|||
42.
|
14.03.2013
|
4
|
Associative
memories
|
43.
|
15.03.2013
|
1
|
Secondary
storage devices
|
44.
|
20.03.2013
|
3
|
Unit – V: Accessing I/O devices
|
45.
|
20.03.2013
|
8
|
Programmed
Input/Output
|
46.
|
21.03.2013
|
4
|
Interrupts
|
47.
|
22.03.2013
|
1
|
Direct
Memory Access
|
48.
|
27.03.2013
|
3
|
Direct
Memory Access
|
49.
|
27.03.2013
|
8
|
Buses
|
50.
|
28.03.2013
|
4
|
Interface
circuits
|
51.
|
03.04.2013
|
3
|
Standard I/O Interfaces (PCI, SCSI,
USB)
|
52.
|
03.04.2013
|
8
|
Standard
I/O Interfaces (PCI, SCSI, USB)
|
53.
|
04.04.2013
|
4
|
I/O devices
and processors
|
54.
|
05.04.2013
|
1
|
I/O devices
and processors
|
CYCLE TEST – III (15.04.2013 – 17.04.2013)
|
Faculty in- charge
HOD/CSE PRINCIPAL
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