CS2354 ADVANCED COMPUTER ARCHITECTURE QUESTION PAPERS

CS2354 ADVANCED COMPUTER ARCHITECTURE APRIL/MAY 2011  ANNA UNIVERSITY QUESTION PAPER QUESTION BANK IMPORTANT QUESTIONS 2 MARKS AND 16 MARKS

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2011.

Sixth Semester

Computer Science and Engineering

CS 2354 — ADVANCED COMPUTER ARCHITECTURE

(Regulation 2008)

Time : Three hours Maximum : 100 marks

Answer ALL questions.

PART A — (10 × 2 = 20 marks)

1. What is instruction level parallelism?
2. What are the advantages of loop unrolling?
3. What are the limitations of VLIW?
4. What is the use of branch-target buffer?
5. Distinguish between shared memory multiprocessor and message-passing multiprocessor.
6. Differentiate multithreading computers from multiprocessor systems
7. Define the terms cache miss and cache hit.
8. What is RAID?
9. What is a multi-core processor?
10. What is a cell processor?

PART B — (5 × 16 = 80 marks)

11. (a) (i) Explain the data and name dependencies with suitable example. (10)
(ii) Discuss about the benefits and limitations of static branch prediction and dynamic branch prediction (6)

Or

(b) Briefly explain how to overcome data hazards with dynamic scheduling using Tomasula’s approach. (16)
12. (a) (i) Describe the architecture of Itanium processor with the help of a block diagram. (8)
(ii) Explain how ILP is achieved in EPIC processors (8)

Or

(b) (i) Describe the architectural features of IA64 processor in detail.(8)
(ii) What are the advantages and disadvantages of software-based and hardware-based speculation mechanism? (8)
13. (a) (i) Briefly compare instruction level parallelism with thread-level parallelism. (8)
(ii) Explain the basic architecture of a distributed memory multiprocessor system. (8)
Or
(b) (i) Explain various memory consistency models in detail. (10)
(ii) What is multithreading and what are the advantages of multithreading? (6)
14. (a) What is meant by cache coherence problem? Describe various protocols for cache coherence. (16)

Or

(b) Briefly explain various I/O performance measures. (16)
15. (a) (i) Describe the architecture of typical CMT processor. (8)
(ii) Discuss the design issues for simultaneous multithreading. (8)

Or

(b) (i) Explain the architectural features of IBM cell processor in detail. (10)
(ii) Briefly compare SMT and CMP architectures. (6)

 

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011

Sixth Semester

Computer Science and Engineering

CS 2354 — ADVANCED COMPUTER ARCHITECTURE

(Regulation 2008)

Time : Three hours Maximum : 100 marks

Answer ALL questions

PART A — (10 × 2 = 20 marks)

1. What is loop unrolling? and what are its advantages?  
2. Differentiate between static and dynamic branch prediction approaches.  
3. What is fine-grained multithreading and what is the advantage and disadvantages of fine-grained multithreading? 
4. What a VLIW processor?  
5. What is sequential consistency?  
6. State the advantages of threading. 
7. Differentiate between write-through cache and snoopy cache.  
8. Compare SDRAM with DRAM.  
9. What is multi–core processor and what are the application areas of multi-core processors?  
10. What is a Cell Processor? 
PART B — (5 × 16 = 80 marks)  
11. (a) Briefly describe any techniques to reduce the control hazard stalls. (16)  
Or  
(b) (i) Discuss about any two compiler techniques for exposing ILP in detail. (8)  
(ii) Explain how ILP is achieved using dynamic scheduling. (8)  

12. (a) (i) Describe the architectural features of IA 64 Processors in detail. (10)  
(ii) Explain the architecture of a typical VLIW processor in detail. (6)  
Or  
(b) (i) Describe the architectural features of Itanium Processor. (10) 
  (ii) Explain how instruction level parallelism is achieved in EPIC processor. (6)  

13. (a) (i) Describe the basic structure of a centralized shared-memory multiprocessor in detail. (6) 
(ii) Describe the implementation of directory-based cache coherence protocol. (10)  
Or  
(b) (i) What are the advantages and disadvantages of distributed-memory Multiprocessors? Describe the basic structure of a distributedmemory multiprocessor in detail. (8)  
(ii) Describe sequential and relaxed consistency model. (8)  

14. (a) (i) With suitable diagram, explain how virtual address is mapped to L2 cache address. (10) (ii) Discuss about the steps to be followed in designing I/O system. (6) 
 Or  
(b) Describe the optimizations techniques used in compilers to reduce cache miss rate. (16)  

15. (a) (i) Describe the features of SUN CMP architecture in detail. (6)  
(ii) What are Multi Core processors? Explain how a multi core processors works. (10)  
Or  
(b) (i) Discuss about the SMT kernel structure in detail. (8)  
(ii) Describe the architecture of the IBM Cell Processor in detail. (8)

M.E/M.Tech DEGREE EXAMINATION, JUNE 2010

First Semester

Computer Science and Engineering

CS9211 – COMPUTER ARCHITECTURE

(Common to M.Tech - Information Technology)

        (Regulation 2009)

Time: Three hours                                                                               Maximum: 100 Marks

                                                     Answer all the questions

                                                    Part A – (10*2=20 Marks)

1.      State the principle of locality and its types.

2.      What are the choices for encoding instruction set.

3.      What is speculation? Give an example.

4.      Mention the effects of imperfect alias analysis.

5.      What is loop unrolling?

6.      Give the uses of sentinel.

7.      Define multiprocessor cache coherence.

8.      What are the approaches used for multithreading?

9.      Which block should be replaced on a cache Miss?

10.  How is cache performance improved?

    Part B – (5*16=80 Marks)

11.  (a)(i)Explain the operations designed for media and signal processing. (10)

    (ii)Explain the ways in which a computer architect can help the compiler writer. (6)

                                                            (Or)

(b)(i)Discuss the addressing modes used for signal processing instructions. (7)

     (ii)Describe the addressing modes and instructions designed for control flow. (9)

12.  (a)Explain the techniques to overcome data hazards with dynamic scheduling. (16)

(Or)

(b)Describe the limitations of Instruction level Parallelism. (16)

13.  (a)(i)Explain the basic VLIW approach used for static multiple issues. (8)

    (ii)Enumerate the crosscutting issues in hardware and s/w speculation mechanisms. (8)

                                                            (Or)

(b)(i)Explain the hardware support for exposing more parallelism at compile time. (8)

    (ii)Describe the basic compiler techniques for exposing ILP. (8)

14.  (a)(i)Describe the design challenges in SMT processors. (8)

    (ii)Discuss the performance of shared memory multiprocessors. (8)

                                                            (Or)

(b)(i)Explain synchronization mechanisms designed for large scale multiprocessors. (9)

    (ii)Discuss the details of memory consistency models. (7)

15.  (a)(i)Explain the concept of miss penalty and out of order execution in processors. (6)

    (ii)Discuss the methods of interface between CPU and memory. (10)

                                                            (Or)

(b)Discuss in detail the different levels of RAID. (16)

M.E/M.Tech DEGREE EXAMINATION, JANUARY 2010

First Semester

Computer Science and Engineering

CS9211 – COMPUTER ARCHITECTURE

(Common to M.Tech - Information Technology)

        (Regulation 2009)

Time: Three hours                                                                               Maximum: 100 Marks

                                                     Answer all the questions

                                                    Part A – (10*2=20 Marks)

1.      What is hazard? State its types.

2.      Mention the techniques available to measure the performance.

3.      What is dynamic scheduling?

4.      Give the limitation of ILP.

5.      Distinguish between hardware and software speculation mechanisms.

6.      What is static branch prediction?

7.      What are the synchronization issues?

8.      What is multithreading?

9.      Define cache miss penalty?

10.  What is RAID?

                                        Part B – (5*16 = 80 Marks)

11.  (a)How does one classify ISA? Discuss their design issues. (16)

(Or)

(b)What is pipelining? Explain various hazards involved in implementing pipelining. (16)

12.  (a)Explain the instruction level parallelism with dynamic approaches. (16)

(Or)

(b)What is dynamic hardware prediction? Explain it in detail. (16)

13.  (a)Explain the different hardware support for exposing ILP. (16)

(Or)

(b)Explain the different hardware support for more parallelism. (16)

14.  (a)Explain distributed shared memory architecture with necessary life cycle diagram. (16)

(Or)

(b)(i)Differentiate software and hardware multithreading approaches. (8)

   (ii)Explain the models of memory consistency. (8)

15.  (a)How does one reduce cache miss penalty and miss rate? Explain. (16)

(Or)

(b)What are the ways available to measure the I/O performance? Explain each of them in detail. (16)